The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. An MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain regions.
The gain of an MOS transistor, usually defined by the transconductance (gm), is proportional to the mobility (μ) of the majority carrier in the transistor channel. The current carrying capability and hence the performance of an MOS transistor is proportional to the mobility of the majority carrier in the channel. The mobility of holes, the majority carrier in a P-channel MOS (PMOS) transistor, and the mobility of electrons, the majority carrier in an N-channel MOS (NMOS) transistor, can be enhanced by applying an appropriate stress to the channel. The known stress engineering methods greatly enhance circuit performance by increasing device drive current without increasing device size and device capacitance. It is known, for example, that a tensile stress liner applied to an NMOS transistor induces a longitudinal stress in the channel and enhances the majority carrier electron mobility, but a tensile stress liner applied to a PMOS transistor results in a decrease in majority carrier hole mobility. Similarly, a compressive stress liner applied to a PMOS transistor induces a compressive stress in the channel and enhances the hole mobility, but if applied to an NMOS transistor the compressive stress liner decreases majority carrier electron mobility.
Various approaches for introducing a stress in a CMOS circuit are known in the art, but suffer from certain drawbacks. In one example, a first tensile stress liner material is deposited over the CMOS circuit, and is subsequently removed from the PMOS using a mask and etch step. Thereafter, a second compressive stress liner material is deposited over the CMOS circuit, and is subsequently removed from the NMOS using another mask and etch step. However, the requirement of multiple material deposition steps, followed by multiple masking and etching steps, increases the overall fabrication cycle time and significantly increases the fabrication cost of the circuit. In another example, embedded SiGe source/drain regions may be fabricated in the circuit in order to compress the channel of the PMOS. However, SiGe is not suitable for use in NMOS circuits, and there is no currently known process scheme that is commercially viable to introduce the same effect in an NMOS circuit. In yet another example, a single stress liner material is deposited over the CMOS circuit, and then the stress over either the NMOS or the PMOS (depending on what type of liner was deposited) is relaxed using an ion implantation step. However, this approach requires a masking step and an implantation step that both need to be highly optimized in order avoid damage the transistor below the stress liner.
Accordingly, it is desirable to provide improved stress enhanced CMOS circuits and methods for their manufacture. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.